1. Field of the Invention
The present invention relates generally to the design of parallel-pipelined data processing equipment and in particular to an apparatus and a method for handling conditional relationships among data items being processed thereby.
2. Description of the Prior Art
A condition register is used in a data processor to record when certain conditional relationships exist in the data being processed. For example, that the value of a data item stored in a first register is greater than that of a data item stored in a second register. Programs being executed by the processor commonly use conditional branch instructions which change the control flow of the programs based on the conditional relationships recorded in a condition register.
In a conditional branch instruction, the processor is instructed to execute a first sequence of instructions if a certain condition is met by the data and to execute a second sequence of instructions if the condition is not met. For example, given two registers A and B, a conditional branch instruction may cause the processor to execute one sequence of instructions if the value held in A is greater than that held in B, and another sequence of instructions otherwise.
In most high performance processors, the existence of a condition is tested by an arithmetic and logic unit (ALU) and the result of the test is stored in a condition register. A program sequencing unit then uses the result in the condition register to change the instruction control flow through the processor as defined by the program being executed. Generally, each processor in a data processing system includes only one condition register, which is not shared with any other processor.
This condition register may be a significant bottleneck in a computer system which is generally able to overlap the execution of multiple instructions. This bottleneck occurs in a pipeline processor when successive instructions need to access the one condition register for conflicting purposes. For example, consider the following set of instructions.
COMPARE (A, B) PA1 BRANCH IF EQUAL PA1 COMPARE (C, D) PA1 BRANCH IF GREATER
The first instruction compares the contents of the registers A and B and sets individual bits in the condition register if A is greater than, equal to, or less than B, respectively. The second instruction changes the control flow of the program (i.e. branches to a new instruction) if the result of the comparison is that the values held in the registers A and B are equal. The third instruction compares the contents of the registers C and D and stores the results of the comparison in the same condition register. Finally, the fourth instruction branches to a new instruction if the greater-than bit is set in the condition register.
In a conventional pipeline processor, which uses only one condition register, it would not be desirable to overlap the execution of the second and third instructions. If this were done, however, the third instruction may change the value in the condition register before the second instruction has completed the branch operation based on the condition value determined by the first instruction.
In many conventional processor designs, separate processing elements are used for fixed-point (i.e. integer) and floating-point (i.e. real) arithmetic. If these processors use a common condition register, the processor should desirably include some mechanism for temporarily suspending one of the processors if it attempts to access the condition register concurrently with the other processor. Alternatively, if each of these processors includes a dedicated condition register, it may be necessary to carefully synchronize the two processors when a conditional branch operation is based on conditions occurring in both processors.
U.S. Pat. No. 4,136,383 to Takesue relates to a data processing system in which a number of ALU's are used in a parallel configuration for concurrent data processing. Each ALU includes circuitry which tests for conditions and a register which holds the test results. The test results for each ALU are channeled to a common control circuit which determines the instruction flow for all of the ALUs.
U.S. Pat. No. 4,748,585 to Chiarulli et al. relates to a processor which includes a plurality of bit-slice sub-processors. While all sub-processors operate in lock-step, each sub-processor is assigned a separate set of operands, a separate operations code and a separate condition code mask. Consequently, the bit-slice sub-processors may be configured in groups where each group performs a different sequence of instructions. Conditional branching for all of the processors is controlled by a combination of condition values generated by all of the processors.
Two articles by T. K. M. Agerwala in the IBM Technical Disclosure Bulletin Vol. 25 No. 1, June 1982 pp 134-137, relate to a reduced instruction set computer (RISC) system which includes separate fixed-point and floating-point processing elements. Both processing elements are sequenced by a common controller. Each processing element has its own internal condition register. Preliminary branch decisions are made by each processor based on the values in these registers. These preliminary decisions may then be combined by a central branch processing unit to generate the final branch decision.